library ieee;
use ieee.std_logic_1164.all;

entity testbench_accu_n is
end testbench_accu_n;

architecture test of testbench_accu_n is

	constant N : integer := 16;

	component accu_n
		generic (N : integer := 16);
		port (
			clk_i 	 : in  std_logic;
			nreset_i : in  std_logic;
			x_i   	 : in  std_logic_vector(N-1 downto 0);
			y_o		 : out std_logic_vector(N-1 downto 0)
		);
	end component;

	signal clk 	  : std_logic;
	signal nreset : std_logic;
	signal x   	  : std_logic_vector(N-1 downto 0);
	signal y	  : std_logic_vector(N-1 downto 0);

begin

	accu_n_inst : accu_n generic map (
		N => N
	) port map (
		clk_i		=> clk, 
		nreset_i 	=> nreset,
		x_i   	 	=> x,
		y_o		 	=> y
	);

	gen_clk : process
	begin
		clk <= '0';
		wait for 10 ns;
		clk <= '1';
		wait for 10 ns;
	end process;

	gen_test : process
	begin

		wait for 100 ns;

		nreset <= '0';

		wait for 20 ns;

		nreset <= '1';
		x	   <= X"0F0F";

		wait for 20 ns;
		
		x	   <= X"F0F0";
		
		wait for 20 ns;
		
		x	   <= X"0050";

		wait for 20 ns;

		x	   <= X"0010";

		wait for 20 ns;

		x	   <= X"0001";

		wait;
	end process;

end test;
